[Concept,4/4] rk3399-generic-ddr3: Enable MMC clock-rate handoff

Message ID 20260329122222.3533806-5-sjg@u-boot.org
State New
Headers
Series vbe: Fix MMC clock handoff for VPL on rk3399 |

Commit Message

Simon Glass March 29, 2026, 12:22 p.m. UTC
  From: Simon Glass <sjg@chromium.org>

Enable CONFIG_MMC_DW_ROCKCHIP_CLK_HANDOFF so that VPL can read the
source clock rate from the bloblist and calculate the correct DW MMC
clock divider for card enumeration.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 configs/rk3399-generic-ddr3_defconfig | 1 +
 1 file changed, 1 insertion(+)
  

Patch

diff --git a/configs/rk3399-generic-ddr3_defconfig b/configs/rk3399-generic-ddr3_defconfig
index 2849889bb8e..0d8cc45be80 100644
--- a/configs/rk3399-generic-ddr3_defconfig
+++ b/configs/rk3399-generic-ddr3_defconfig
@@ -74,6 +74,7 @@  CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_DW_ROCKCHIP_CLK_HANDOFF=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y