From patchwork Sun Mar 29 12:22:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 2073 Return-Path: X-Original-To: u-boot-concept@u-boot.org Delivered-To: u-boot-concept@u-boot.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1774786969; bh=2SFJNYRLoStolvpjSwJMARXo3mblhA8DXDKnzI598DQ=; h=From:To:Date:In-Reply-To:References:CC:Subject:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=fywOeqzaAgKmNufqzCVUXWh4TzXdoklN5JQM4vMu2EHVhQoL2u1u/zRZQzNe/6qxg Z99eSS6yn5KpHBEbJ3Gd1OkbdrQcD37TYGE2OknaR4/zmUF2Ie63XKIhsB3V07f5Zy NEnwgKPvXWd8Xsqg4oNj4Z6LCl4tlgPIusQrQXFPWwQv4N0qh6u5d+8+waWAno+vRr wL5cN1+JNrE92+frP/nWlzq7JHBiN9pKuN36zramNlgmiG3xABXOK2b7PabisaHq6J TvxnzKH6ZicZosayqPpdAvm2myiTiy9ii5SNQ60niT6751YZyNWI1mgy29T5x+ZCZa voaGCLGG6hx+g== Received: from localhost (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id 239FA6A2D9 for ; Sun, 29 Mar 2026 06:22:49 -0600 (MDT) X-Virus-Scanned: Debian amavis at Received: from mail.u-boot.org ([127.0.0.1]) by localhost (mail.u-boot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id GPupeBHqjs8q for ; Sun, 29 Mar 2026 06:22:49 -0600 (MDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1774786968; bh=2SFJNYRLoStolvpjSwJMARXo3mblhA8DXDKnzI598DQ=; h=From:To:Date:In-Reply-To:References:CC:Subject:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=Jy/7RI0fgyO/UgA4vm3ReuYNvPQVRe0AjAtBmXGwN+Z3ZNRc9wtH/C9OBnvXzGw+y lxEkSW9F4p6smagXPOYE+FdHvyCTrNxpPd36i+GHQit+FCNhOkGSBMlVKW/sN9VieU W4k3MOWDyw37zdwA9RCqTMeNW429ZLV8HKtY4LmfVSYvErDTKYoq/PWqLTAY9pH/7q GVtNE2p0RRqPr1jAGxB459sw9OOJ4vAwW2rqIhf5I8+0eHfmXbKaL5LEx99mUaD7Bk YExRH5mPUQ3uwQNUqU3c3rGk8OsbJn1f3SmILehVltclpVtjjXT6SUzcJZAYL5ABkz aCXhvzxNg3jPQ== Received: from mail.u-boot.org (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id 7C8466A2D0 for ; Sun, 29 Mar 2026 06:22:48 -0600 (MDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1774786966; bh=ZW3LcT/1D2nLbP44fDbn/4knD2EyEDXdN52v1w/EFWU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iAjcHNOVo+Pqy8tcrKtTyCApLLMtrFPVzNf8Bd/JEagqgRJlHxX0Svx4hCitoq7Ik /PFjvhfh2jV+j10ZGsZDC59eEIGhMwlVpxxNCIpXYkEJvBMtiGjNvsa6YPvkjNNADe IBXbqDBVkvyo3IDQQvsaV8WueUrl4yQfOam2yPIPrsmh/FlRX4w7LU6mBcEf59LBRl TbBlaiPPkJwLPsHuN/iHTfhh4c8UcvIyvnU7grMdK5xjqhxYVCDjcPCbFkgIRPmTT8 Mb4zRh5lt8cSHRKmRNH8ZJEocnf4tav8+PYqW1/X1TkQghzux5/om1t6HGPNZ8lfCB KqSAff+qSUxNA== Received: from localhost (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id 0B8086A2C7; Sun, 29 Mar 2026 06:22:46 -0600 (MDT) X-Virus-Scanned: Debian amavis at Received: from mail.u-boot.org ([127.0.0.1]) by localhost (mail.u-boot.org [127.0.0.1]) (amavis, port 10026) with ESMTP id 4Q58MhFg4Hzd; Sun, 29 Mar 2026 06:22:45 -0600 (MDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1774786965; bh=Qm1Rr+jh1Xn1ixG6mL5iLEMC8p5LaXDpgGj9kQ7QHEw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L8smIZiLFy0PRFXwViHVq75kQYMppr3YSpy0qwN4/tuw5zL5OCQtHflcOfPS58MBD uCQlwOGGYC6U95YywwxaV8EVmYA/1i3LPoljEEMDTd4vQTNjF/ArLNS7phu0vaJj/h xUrQDls47zCqIpOmXS57ltqad3jLQ8AhLEZRSDoKkVadB4/BcarcJL9iARUOwtYLKg Au3pRhb2G4jxrRW+7PpmDzgegFqouCke7GMFmbWf21gsyxAtKxjK4DWzP+v88G5R6G WYvdfeX8vDR6L3jXjEinbdYCNWtgmi2fHtMmqUmFL+fJ8TEvHY9as8LM/BF+W8ttnl FCl0TCjLTjJ0A== Received: from u-boot.org (unknown [73.34.74.121]) by mail.u-boot.org (Postfix) with ESMTPSA id 70F1C6A269; Sun, 29 Mar 2026 06:22:45 -0600 (MDT) From: Simon Glass To: U-Boot Concept Date: Sun, 29 Mar 2026 06:22:18 -0600 Message-ID: <20260329122222.3533806-4-sjg@u-boot.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260329122222.3533806-1-sjg@u-boot.org> References: <20260329122222.3533806-1-sjg@u-boot.org> MIME-Version: 1.0 Message-ID-Hash: 76EZJ3OH2IPH6OXMU2AI5PPHFDK64PJC X-Message-ID-Hash: 76EZJ3OH2IPH6OXMU2AI5PPHFDK64PJC X-MailFrom: sjg@u-boot.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Simon Glass X-Mailman-Version: 3.3.10 Precedence: list Subject: [Concept] [PATCH 3/4] mmc: rockchip_dw_mmc: Pass clock rate via bloblist List-Id: Discussion and patches related to U-Boot Concept Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Simon Glass When the CLK framework is not available (e.g. in VPL), the DW MMC driver cannot set the source clock rate, so get_mmc_clk() returns the requested frequency. The DW MMC core then uses bypass mode (divider=0), running the bus at whatever rate the CRU is configured to from a previous phase. If that rate is high (e.g. 50 MHz from a data transfer), card enumeration at 400 KHz fails. Fix this by saving the clock rate to the bloblist when CLK is available, and reading it back when CLK is not. This allows the DW MMC core to calculate the correct clock divider based on the actual source clock rate configured by the previous boot phase. This is controlled by a new CONFIG_MMC_DW_ROCKCHIP_CLK_HANDOFF Kconfig option. Signed-off-by: Simon Glass --- drivers/mmc/Kconfig | 9 +++++++++ drivers/mmc/rockchip_dw_mmc.c | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 4c46df0ffb8..01d7025ce4d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -292,6 +292,15 @@ config MMC_DW_ROCKCHIP SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as removeable SD and micro-SD cards. +config MMC_DW_ROCKCHIP_CLK_HANDOFF + bool "Pass MMC clock rate between boot phases via bloblist" + depends on MMC_DW_ROCKCHIP && BLOBLIST + help + When enabled, the DW MMC source clock rate is saved to the + bloblist after being configured. A later boot phase that lacks + CLK support can read this rate and use it to calculate the + correct clock divider, rather than assuming bypass mode. + config MMC_SDHCI_ADI bool "ADI SD/MMC controller support" depends on ARCH_SC5XX diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 7a72abaa38a..be6436dbe7d 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include @@ -50,8 +51,38 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { + /* + * If CLK is not available (e.g. VPL), use the rate saved + * by the previous phase via bloblist. The CRU is still + * configured from that phase, so the DW MMC core can + * calculate the correct clock divider. + */ + if (!CONFIG_IS_ENABLED(CLK) && + IS_ENABLED(CONFIG_MMC_DW_ROCKCHIP_CLK_HANDOFF)) { + u32 *ratep; + + ratep = bloblist_find(BLOBLISTT_U_BOOT_MMC_CLK, + sizeof(*ratep)); + if (ratep) + return *ratep; + } debug("%s: err=%d\n", __func__, ret); - return 0; + return freq; + } + + /* Save the source clock rate for the next phase */ + if (IS_ENABLED(CONFIG_XPL_BUILD) && + IS_ENABLED(CONFIG_MMC_DW_ROCKCHIP_CLK_HANDOFF)) { + u32 *ratep; + + ratep = bloblist_ensure(BLOBLISTT_U_BOOT_MMC_CLK, + sizeof(*ratep)); + if (ratep) { + ulong rate = clk_get_rate(&priv->clk); + + if (!IS_ERR_VALUE(rate)) + *ratep = rate; + } } return freq;