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[Concept] riscv: dts: jh7110: Exclude PLL clock controller from SPL

Message ID 20260327122515.2705629-1-sjg@u-boot.org
State New
Headers
Series [Concept] riscv: dts: jh7110: Exclude PLL clock controller from SPL |

Commit Message

Simon Glass March 27, 2026, 12:25 p.m. UTC 
  From: Simon Glass <sjg@chromium.org>

Adding bootph-pre-ram to the pllclk node causes it to be included in
the SPL device tree. The PLL clock controller is not previously present
in SPL, and its inclusion changes the clock-tree behaviour during early
boot: the clock framework now resolves and configures PLL-based clock
parents for syscrg, which disrupts MMC clock setup and causes a
partition-read failure (error -ENOSYS) when SPL tries to boot from MMC.

Remove the bootph-pre-ram property from pllclk via the U-Boot DTS
overlay so that the SPL clock tree matches the previous working state.

Fixes: 7f5174739645f ("riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader")
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/riscv/dts/starfive-visionfive2-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
index 33a58349752..2e079867b4b 100644
--- a/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
@@ -49,3 +49,7 @@ 
 &sys_syscon {
 	bootph-pre-ram;
 };
+
+&pllclk {
+	/delete-property/ bootph-pre-ram;
+};