From patchwork Mon Feb 16 01:35:05 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1897 Return-Path: X-Original-To: u-boot-concept@u-boot.org Delivered-To: u-boot-concept@u-boot.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1771205778; bh=VqAtHEvCiO8UIGhDAYHVPxuWO/O7f3KvQYBX4FAAvL0=; h=From:To:Date:In-Reply-To:References:CC:Subject:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=WcqRbGxXmCVYDqHmLFzmTtfP/3mrrO1dRimNCvIcyho16XMxj6t84lf4ZY5AYUntZ 3ita3V5jxiaSKQNrZcizrDBL25f4j23YZxvHuxz5rxLP11cJNu2rdZW0l73cvmLuFP JjN/4xbt2Mb1/kAGxzaEIgKmzhjrQo2izgB0UDHwHKxSG26Yel4UDIX5yYOSzIczxd +d6x/bzt6FiKm9jVnEr7R724M0KvSQmm8wyfO7yu2z40hj9z6/qkIQ7WfYSb5rCZMq xwPpd2yP0zx0tvJ1nQgEyxzTBkNiZ1NwrywspnFgoxJ1ND+pBEsFlsysS6kFH+hV1z YMXx3Inr6EJtg== Received: from localhost (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id 6835A69BE5 for ; Sun, 15 Feb 2026 18:36:18 -0700 (MST) X-Virus-Scanned: Debian amavis at Received: from mail.u-boot.org ([127.0.0.1]) by localhost (mail.u-boot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id ZcrMQWK5Pbwh for ; Sun, 15 Feb 2026 18:36:18 -0700 (MST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1771205777; bh=VqAtHEvCiO8UIGhDAYHVPxuWO/O7f3KvQYBX4FAAvL0=; h=From:To:Date:In-Reply-To:References:CC:Subject:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=wPSU7jV9ZND03hMjm4sUrk3NtKCmob707giUYuinSC7BCsnph7em5h3itM1IaxWMH 8BtMhsXbfugG+kYSBETzzQaebJTqoJz7qYxIrBuq37Am8QD+UPdg1Q8GwR4sz9ijcH TAq3x/usqboHg9BOeaDy/pgeyH4hWLeshoSziZ80yBOWDjny0Xoprv1BajOhdaj78H 2qwGBMZoe8amCIf+toyb3d5yzNe28viWWz8KONJnB8PIowzNH4lUR+AS9C3PokFnVO 6+5bEPChY858sWMWfBNnX7uLnzqMI00StZxKM/ki9+KNkmYRuJjuAkr7aSnjfY3f1S g/yNLCQzBnK2g== Received: from mail.u-boot.org (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id CE8BA69BCC for ; Sun, 15 Feb 2026 18:36:17 -0700 (MST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1771205775; bh=TYlEU61zSZX0Umtaf4vTjm3G9xyjukgiqsEClv4ss0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZNmIMQ2LclG9yXi3JJizl6x1ExXr2/hzaGOCVs0iidD/QTqzyDsbQY4rJcE4SIqIm jjRoknv51fQ3EeiV9rGMgGFoKiCqz/rMtvgonAFPPn1SW2STXmFWMW8nCRfB/KEYOG hr/K2YWSaQu84DPwRkL6Y5m18V7abl8zU3QQjC1/aXLJHO15J9nukXhubRzkP9p6Lf C4fVEBaEhgXYP1u+yFTQbGNzMBjmHhw17n38DuwaGzJnGsyWA7eETyQ8JdF52fJfis qkjt1bB0Pj9udm8t52F7/mdrzK6DYsrRMBykBLgiPnsAUfPEqeYx1ifgUhXjgwJ20k 3f2QOUoFWmL1g== Received: from localhost (localhost [127.0.0.1]) by mail.u-boot.org (Postfix) with ESMTP id E248569BCC; Sun, 15 Feb 2026 18:36:15 -0700 (MST) X-Virus-Scanned: Debian amavis at Received: from mail.u-boot.org ([127.0.0.1]) by localhost (mail.u-boot.org [127.0.0.1]) (amavis, port 10026) with ESMTP id P0Xj_8Ohyn_w; Sun, 15 Feb 2026 18:36:15 -0700 (MST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=u-boot.org; s=default; t=1771205773; bh=Jv0CVkZbijDPPDmuVUF5flt7aIwwNqQytmHhNavQsRA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sQZRc6p6ANEHQErqi8un1s5QC1d6+1GgSJx2xo0YS1QcanxcXciqA/4DiuvQsvbUr dJNoxEzXQ4Odc948/IHse/CjbMPca+ladwboOdKhrI5Azsymzjm+yiCmiGlvA9Kklm Sw9hnmAZeXg5nrEcJN2NoTojBp/1C1Xu7W0GFsoCOCPOF7ggy2dg5/MHBsNH4oz3Tl C/T7cQ43+f9qb6JZpMm/go5CsQluRdKYAJXhzrKqYUR9F0tl+Iq9Mgq+CYs9hFEHC4 h+80d6Kxhj923ougOZwYh9fHQRS/2mKnhQRdY7vLdbEgEvLkf++kNG68yT6Siocqdr GxIaXgtddU6uQ== Received: from u-boot.org (unknown [73.34.74.121]) by mail.u-boot.org (Postfix) with ESMTPSA id 7125B69B01; Sun, 15 Feb 2026 18:36:13 -0700 (MST) From: Simon Glass To: U-Boot Concept Date: Sun, 15 Feb 2026 18:35:05 -0700 Message-ID: <20260216013511.4079770-18-sjg@u-boot.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260216013511.4079770-1-sjg@u-boot.org> References: <20260216013511.4079770-1-sjg@u-boot.org> MIME-Version: 1.0 Message-ID-Hash: CTDSJB6ITP26RDRO4XOXP47WXR6VJN7O X-Message-ID-Hash: CTDSJB6ITP26RDRO4XOXP47WXR6VJN7O X-MailFrom: sjg@u-boot.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Simon Glass , "Claude Opus 4 . 6" X-Mailman-Version: 3.3.10 Precedence: list Subject: [Concept] [PATCH 17/17] ulib: scripts: Add RISC-V support to build-qemu List-Id: Discussion and patches related to U-Boot Concept Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Simon Glass The build-qemu script accepts --arch riscv via build_helper's argument parser but raises ValueError since no riscv block exists. Add RISC-V support with: - Board names qemu-riscv64/qemu-riscv32 (and _spl variants) - QEMU binary selection (qemu-system-riscv64/riscv32) - Machine type 'virt' with TCG acceleration - Tianocore firmware path (RISCV_VIRT_CODE.fd) - virtio-gpu-pci display setup (shared with arm, since the virt machine has no native VGA) Co-developed-by: Claude Opus 4.6 Signed-off-by: Simon Glass --- scripts/build-qemu | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/scripts/build-qemu b/scripts/build-qemu index 4f77eb88167..5c69457647e 100755 --- a/scripts/build-qemu +++ b/scripts/build-qemu @@ -9,7 +9,7 @@ It assumes that board config - your OS images are in ${imagedir}/{distroname}/ -So far the script supports only ARM and x86 +So far the script supports ARM, RISC-V and x86 """ import argparse @@ -122,6 +122,8 @@ class BuildQemu: elif args.use_tianocore: if args.arch == 'arm': bios_override = Path(self.tiano, 'OVMF-pure-efi.aarch64.fd.64m') + elif args.arch == 'riscv': + bios_override = Path(self.tiano, 'RISCV_VIRT_CODE.fd') else: bios_override = Path(self.tiano, 'OVMF-pure-efi.x64.fd') if not bios_override.exists(): @@ -156,6 +158,23 @@ class BuildQemu: self.board = 'qemu_arm64' self.helper.qemu = 'qemu-system-aarch64' self.qemu_extra.extend(['-cpu', 'cortex-a57']) + elif args.arch == 'riscv': + if args.xpl: + self.board = 'qemu-riscv64_spl' + default_bios = 'u-boot.bin' + else: + self.board = 'qemu-riscv64' + default_bios = 'u-boot.bin' + self.helper.qemu = 'qemu-system-riscv64' + self.qemu_extra.extend(['-machine', 'virt']) + if not args.kvm: + self.qemu_extra.extend(['-accel', 'tcg']) + if self.helper.bitness == 32: + if args.xpl: + self.board = 'qemu-riscv32_spl' + else: + self.board = 'qemu-riscv32' + self.helper.qemu = 'qemu-system-riscv32' elif args.arch == 'x86': self.board = 'qemu-x86' default_bios = 'u-boot.rom' @@ -291,7 +310,7 @@ class BuildQemu: # SCT usually runs headlessly if self.args.serial_only or self.args.sct_seq: qemu_cmd.extend(['-display', 'none']) - elif self.args.arch == 'arm': + elif self.args.arch in ('arm', 'riscv'): qemu_cmd.extend(['-device', 'virtio-gpu-pci']) qemu_cmd.extend(['-device', 'qemu-xhci', '-device', 'usb-kbd', '-device', 'usb-tablet', '-device', 'usb-mouse'])